1. Field of the Invention
The present invention relates to a nonvolatile memory, and particularly relates to an EEPROM (Electrically Erasable and Programmable Read Only Memory).
2. Description of the Related Art
An EEPROM is known as a nonvolatile memory capable of electrically programming and erasing data. A “single poly EEPROM” is a type of the EEPROM, which does not have a stacked gate but a single-layer gate. Such a single poly EEPROM is disclosed, for example, in the following patent documents.
In an EEPROM described in Japanese Laid-Open Patent Application JP-P2000-340773, an N+ diffusion layer formed in a surface portion of a semiconductor substrate functions as a control gate. The N+ diffusion layer overlaps a single-layer gate (floating gate) formed on the semiconductor substrate. The single-layer gate also overlaps a tunnel region in the semiconductor substrate, and charges are injected into the single-layer gate from the tunnel region. Furthermore, the EEPROM has a MOS transistor that uses the single-layer gate as a gate electrode. The above-mentioned tunnel region is a part of a source or a drain of the MOS transistor.
An EEPROM described in Japanese Laid-Open Patent Application JP-P2001-185633 has: a first N-well and a second N-well which are formed in a substrate; a single-layer gate (floating gate) formed on the substrate; and a read transistor. The first N-well and the single-layer gate overlap each other through a gate insulating film to form a first capacitor. The second N-well and the single-layer gate overlap each other through a gate insulating film to form a second capacitor. A P-type diffusion layer and an N-type diffusion layer are formed in each of the first and the second N-wells. The P-type diffusion layer is formed around the single-layer gate, while the N-type diffusion layer is formed away from the single-layer gate. Charges are injected into the single-layer gate through the gate insulating film at the first capacitor or the second capacitor.
An EEPROM described in U.S. Pat. No. 6,788,574 has: a first N-well and a second N-well which are formed in a substrate; a single-layer gate (floating gate) formed on the substrate; and a read transistor. The first N-well and the single-layer gate overlap each other through a gate insulating film to form a tunneling capacitor. The second N-well and the single-layer gate overlap each other through a gate insulating film to form a coupling capacitor. A P-type diffusion layer and an N-type diffusion layer are formed in each of the first and the second N-wells. The P-type diffusion layer and the N-type diffusion layer are abutted to each other in each N-well. Charges are injected into the single-layer gate through the gate insulating film at the tunneling capacitor.
Japanese Laid-Open Patent Application JP-H06-334190 discloses a technique in which charges are injected into a single-layer gate through a gate insulating film at not the tunneling capacitor but at a transistor.
FIG. 1 shows a structure of an EEPROM cell described in the Japanese Laid-Open Patent Application JP-H06-334190. In FIG. 1, an N-well 104 is formed in a P-type semiconductor substrate 101, and a single-layer polysilicon (floating gate) 108 is formed on the P-type semiconductor substrate 101 through a gate insulating film. An NMOS transistor is formed on the P-type semiconductor substrate 101, while a PMOS transistor is formed on the N-well 104. More specifically, the NMOS transistor consists of N+ diffusion layers (source/drain) 102a, 102b and a gate electrode 103. On the other hand, the PMOS transistor consists of P+ diffusion layers (source/drain) 105a, 105b, an N+ diffusion layer 106 and a gate electrode 107. The above-mentioned single-layer polysilicon (floating gate) 108 is not only the gate electrode 103 of the NMOS transistor but also the gate electrode 107 of the PMOS transistor.
In the EEPROM cell thus constructed, charges are transferred with respect to the floating gate 108 through the gate insulating film of the NMOS transistor, by applying predetermined potentials to respective of terminals 109, 110 and 111. The PMOS transistor serves as a control gate. When electrons are injected into the floating gate 108, the CHE (channel hot electron) method can be employed, for example. On the other hand, when electrons are ejected from the floating gate 108, the FN (Fowler-Nordheim) tunneling method can be employed, for example.
FIG. 2 shows the case where electrons are ejected from the floating gate 108 in accordance with the FN tunneling method. In this case, a high potential Ve is applied to the source/drain 102a, 102b of the NMOS transistor through the terminals 109 and 110, while a ground potential is applied to the source/drain 105a, 105b and the N+ diffusion layer 106 of the PMOS transistor through the terminal 111. Thus, a strong electric field is generated between the gate electrode 103 and the source/drain 102a, 102b. As a result, electrons are ejected from the gate electrode 103 to the source/drain 102a, 102b due to the FN tunneling.